Senior RTL / FPGA Design Engineer

Experience: 6+ Years
Location: Bengaluru
Work Mode: Work from Office
Employment Type: Full-Time

Job Summary

We are looking for an experienced Senior RTL / FPGA Design Engineer with 6+ years of hands-on experience in RTL design and FPGA development. The ideal candidate should be capable of independently taking ownership of digital design blocks from specification and micro-architecture through RTL implementation, synthesis, timing closure, and successful FPGA or silicon delivery.

The role involves close collaboration with architecture, verification, physical design, and system teams to develop high-quality, reusable, and timing-clean RTL.

Key Responsibilities

• Own RTL design and development from specification and micro-architecture through implementation and sign-off.
• Develop clean, synthesizable, scalable, and reusable Verilog/SystemVerilog RTL.
• Design and implement digital blocks including FSMs, pipelines, FIFOs, arbitration logic, reset architectures, and clock-domain crossings.
• Work with FPGA toolchains such as Xilinx Vivado or Intel Quartus for synthesis, implementation, constraints, timing analysis, and debugging.
• Develop, review, and debug SDC timing constraints.
• Analyze timing reports and drive timing closure for FPGA designs.
• Perform and debug lint and CDC analysis using tools such as SpyGlass, Meridian, or equivalent.
• Investigate violations, identify root causes, and implement appropriate RTL or constraint fixes rather than relying only on waivers.
• Support FPGA bring-up, hardware debugging, and integration.
• Collaborate with verification teams to define verification requirements and debug RTL and gate-level issues.
• Review RTL, participate in design reviews, and mentor junior engineers when required.
• Debug issues across RTL, simulation, synthesis, STA, and FPGA hardware.
• Ensure designs meet quality, performance, area, power, and timing requirements.

Mandatory Skills

• 6+ years of hands-on RTL design experience.
• Strong expertise in Verilog/SystemVerilog.
• Proven experience independently delivering RTL blocks from specification to working FPGA or silicon.
• Strong experience with at least one FPGA toolchain:
  • Xilinx Vivado, or
  • Intel Quartus
• Hands-on experience with:
  • Synthesis and implementation
  • Timing analysis and closure
  • Constraint development and debugging
  • FPGA debugging
• Strong knowledge of SDC timing constraints.
• Experience with Lint and CDC tools, such as SpyGlass, Meridian, or equivalent.
• Strong understanding of:
  • FSM design
  • Pipelining
  • Arbitration
  • FIFO design
  • Clock Domain Crossing (CDC)
  • Reset architecture
  • Synchronous/asynchronous interfaces
• Good understanding of digital design fundamentals and RTL coding best practices.
• Experience working closely with verification teams and debugging RTL/gate-level issue